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INTEGRATED CIRCUITS
PCA9559 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
Product specification Supersedes data of 1999 Oct 20 2000 Jan 31
Philips Semiconductors
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
FEATURES
*5-bit 2-to-1 multiplexer, 1-bit latch *6-bit internal non-volatile register *Internal non-volatile register programmable and readable via I2C bus *Override input forces all outputs to logic 0 *5 open drain multiplexed outputs *1 open drain non-multiplexed (latched) output *5V and 2.5V tolerant inputs *Useful for `jumperless' configuration of PC motherboards *2 address pins, allowing up to 4 devices on the I2C bus
DESCRIPTION
The primary function of the 5-bit multiplexer, 1-bit latch is to enable system configuration.
PIN CONFIGURATION
2 IC
SCL SDA A1 A0
1 2 3 4 5 6 7 8 9
20 VCC 19 WP 18 OVERRIDE # 17 NON_MUXED_OUT 16 MUX_OUT A 15 MUX_OUT B 14 MUX_OUT C 13 MUX_OUT D 12 MUX_OUT E 11 MUX_SELECT
I2C
MUX_IN A MUX_IN B MUX_IN C MUX_IN D MUX_IN E
GND 10
SW00216
ORDERING INFORMATION
PACKAGES 20-Pin Plastic TSSOP TEMPERATURE RANGE 0C to +70C ORDER CODE PCA9559 PW DH DRAWING NUMBER SOT360-1
FUNCTIONAL DESCRIPTION
When the MUX_SELECT signal is logic 0, the multiplexer will select the data from the non-volatile register to drive on the MUX_OUT pins. When the MUX_SELECT signal is logic 1, the multiplexer will select the MUX_IN lines to drive on the MUX_OUT pins. The MUX_SELECT signal is also used to latch the NON_MUXED_OUT signal which outputs data from the non-volatile register. The NON_MUXED_OUT signal latch is transparent when MUX_SELECT is in a logic 0 state, and will latch data when MUX_SELECT is in a logic 1 state. When the active-LOW OVERRIDE# signal is set to logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will be driven to logic 0. This information is summarized in Table 1. The Write Protect (WP) input is used to control the ability to write the contents of the 6-bit non-volatile register. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile register. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile register. The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C bus (described in the next section). The OVERRIDE#, WP, MUX_IN, and MUX_SELECT signals have internal pullup resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures.
FUNCTION TABLE
OVERRIDE# MUX_SELECT
MUX_OUT OUTPUTS All 0's MUX_IN inputs From nonvolatile register MUX_IN inputs
NON_MUXED_OUT OUTPUT All 0's Latched NON_MUXED_OUT 1 From non-volatile register From non-volatile register
0 0
0 1
1
0
1
1
NOTE: 1. NON_MUXED_OUT state will be the value present on the output at the time of the MUX_SELECT input transitioned from a logic 0 to a logic 1 state.
2000 Jan 31
2
853-2181 23063
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
PIN DESCRIPTION
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL I2C SCL I2C SDA A1 Address A0 Address MUX_IN A MUX_IN B MUX_IN C MUX_IN D MUX_IN E GND MUX_SELECT MUX_OUT E MUX_OUT D MUX_OUT C MUX_OUT B MUX_OUT A NON_MUXED_OUT OVERRIDE# WP VCC Open drain outputs from non-volatile memory Forces all outputs to logic 0 Non-volatile register write-protect Positive voltage rail Open drain multiplexed outputs Ground Selects MUX_IN inputs or register contents for MUX_OUT outputs External inputs to multiplexer Serial I2C bus clock Serial bi-directional I2C bus data A1 A0 FUNCTION
I2C INTERFACE
Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) has 5 fixed bits and two user-programmable bits followed by a 1-bit read/write value which determines the direction of the data transfer.
MSB LSB
1
0
0
1
1
A1
A0
R/W#
SW00218
Figure 1.
I2 C
Address Byte
Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read from the register if the bit is logic 1. The four high-order bits are latched outputs, while the four low order bits are multiplexed outputs (Figure 2). NOTE: 1. To ensure data integrity, the non-volatile register must be internally write protected when VCC to the I2C bus is powered down or VCC to the component is dropped below normal operating levels.
MSB
LSB
0
0
Non_muxed Data
Mux Data E
Mux Data D
Mux Data C
Mux Data B
Mux Data A
SW00456
Figure 2. I2C Data Byte
2000 Jan 31
3
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
BLOCK DIAGRAM
10-30k MUX_SELECT
11
18 4 3
OVERRIDE#
A0 A1
100-150k 6-BIT EEPROM LATCH NMO SELECT 2 I C iNTERFACE LOGIC SCL I2C CLOCK 2 SDA I2C DATA
1
17 NON_MUXED_OUT
0
VCC = 20 GND = 10
16 MUX_OUT A
MUX_OUT B 19 WRITE PROTECT OE# 5-BIT 2 to 1 MULTIPLEXER MUX_OUT C
15
14
5 MUX_IN A 6
13 MUX_OUT D
MUX_IN B
7
MUX_OUT E MUX_IN C
12
8
MUX_IN D
9
MUX_IN E
10-30k 1
SW00400
2000 Jan 31
4
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL VCC VI VOUT Tstg PARAMETER DC supply voltage DC input voltage DC output voltage Storage temperature range Note 3 Note 3 CONDITIONS RATING -0.5 to +4.6 -1.5 to VCC +1.5 -0.5 to VCC +0.5 -60 to +150 UNIT V V V C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC PARAMETER DC supply voltage VIL SCL, SCL SDA VIH VOL VOL OVERRIDE#, MUX_IN, , _, MUX_SELECT MUX_OUT, NON MUXED OUT MUX OUT NON_MUXED_OUT dt/dv Tamb VIL VIH IOL IOH Input transition rise or fall time Operating temperature 0 0 IOL= 3 mA IOL= 3 mA IOL= 3 mA IOL= 6 mA -0.5 2.0 CONDITIONS LIMITS MIN 3.0 -0.5 2.7 MAX 3.6 0.9 4.0 0.4 0.6 0.8 4.0 8 100 10 70 UNIT V V V V V V V mA A ns/V C
2000 Jan 31
5
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
DC CHARACTERISTICS
LIMITS SYMBOL Supply VCC ICCL ICCH Supply Voltage Supply Current Supply Current Operating mode ALL inputs = 0 V Operating mode ALL inputs = VCC 3 3.8 10 600 V mA A PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
Input SCL: Input/Output SDA VIL VIH IOL IOL IIH IIL CI Low Level Input Voltage High Level Input Voltage Low Level Output Current Low Level Output Current Leakage Current High Leakage Current Low Input Capacitance VOL = 0.4 VOL = 0.6 VI = VCC VI = GND -0.5 2 3 6 -1.5 -7 -12 -32 10 0.8 VCC + 0.5 V V mA mA A A pF
Override #, WP, Mux_Select IIH IIL CI Mux A E IIH IIL CI A0, A1 Inputs IIH IIL CI Mux_Outputs VOL VOL Low Level Output Current Low Level Output Current (IOL = 100 A) (IOL = 2 mA) 0.4 0.7 V V Leakage Current High Leakage Current Low Input Capacitance VI = VCC VI = GND -1 -1 1 1 10 A A pF Leakage Current High Leakage Current Low Input Capacitance VI = VCC VI = GND -0.166 -0.72 -0.75 -2 10 mA mA pF Leakage Current High Leakage Current Low Input Capacitance VI = VCC VI = GND -20 -86 -100 -267 10 A A pF
Non_Mux_Output VOL VOL NOTES: 1. VHYS is the hysteresis of Schmitt-Trigger inputs (IOL = 100 A) (IOL = 2 mA) 0.4 0.7 V V
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER Memory cell data retention Number of memory cell write cycles SPECIFICATION 10 years min 3,000 cycles min
2000 Jan 31
6
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
AC CHARACTERISTICS
SYMBOL MUX_in MUX_out Tplh Tphl Select MUX_out Tplh Tphl Override Non-MUX_out Tplh Tphl Override MUX_out Tplh Tphl TR TF PF CL I2C Bus tSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSP tSU:STO tR tI CL TW SCL clock frequency Bus free time between a STOP and a START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of SCL clock HIGH period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Data spike time Set-up time for STOP condition Rise time for both SDA and SCL signals (10 - 400 pF bus) Fall time for both SDA and SCL signals (10 - 400 pF bus) Capacitive load for each bus line Write cycle time1 15 10 1.3 600 1.3 600 600 0 100 0 600 20 20 -12 -32 10 -100 50 10 300 300 400 400 kHz s ns s ns ns ns ns ns ns ns ns pF mS Output rise time Output fall time Pull-up resistor for outputs Test load capacitance on outputs 1.0 1.0 1.0 31 21 41 27 3 3 nS nS ns/V ns/V ns/V pF 34 19 43 25 nS nS 30 17 39 22 nS nS 28 16 37 21 nS nS PARAMETER LIMITS MIN. TYP. MAX. UNIT
NOTE: 1. WRITE CYCLE time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I2C Address.
2000 Jan 31
7
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
MUX INPUT VM VM VIN PULSE GENERATOR RT
VCC
VO
tPHL
tPLZ
VO
VOUT D.U.T.
RL
MUX OUTPUT
VM VOL + 0.3V VOL
CL
SV00500
Test Circuit for Open Drain Outputs
Waveform 1.
Open drain output enable and disable times
DEFINITIONS
RL = Load resistor; 1 k CL = Load capacitance includes jig and probe capacitance; 10 pF RT = Termination resistance should be equal to ZOUT of pulse generators.
SW00510
2000 Jan 31
8
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
2000 Jan 31
9
Philips Semiconductors
Product specification
5-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PCA9559
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 01-00 Document order number: 9397 750 06833
Philips Semiconductors
2000 Jan 31 10

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